Multiprocessor systems are now commonly used in environments such as businesses and research. When a processor in a multiprocessor system requests access to the memory, an arbiter is typically utilized to determine which data request is granted and in which order. These requests from the processors and grants from the arbiter are typically carried by the system bus.
In the conventional system, a minimum of five bus cycles are typically required between the time an internal request for data is generated within the processor, and the time which the address for the requested data is reached in the memory. The time required between the internal request and the address being reached in the memory controller is typically referred to as the internal request to memory address latency. It is common to require 13-16 bus cycles between the time a data request is generated within the processor or cache and the time which the data is retrieved. This time period is typically referred to as the read data latency.
What is needed is a system and method for reducing memory read data latency and improving address throughput. The present invention addresses such a need.